1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to a method for fabricating an array of DRAM cells with closely spaced capacitors having reduced parasitic capacitance between adjacent capacitors, and DRAM embedded in integrated circuits.
2. Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are used extensively in the electronics industry, and more particularly in the computer industry for storing data in binary form (1s and 0s) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or chips). Each DRAM circuit (chip) consists in part of an array of individual memory cells that store binary data (bits) as electrical charge on the storage capacitors. Further, the information is stored and retrieved from the storage capacitors by means of switching on or off a single access transistor (via word lines) in each memory cell using peripheral address circuits, while the charge stored on the capacitors is sensed via bit lines and by read/write circuits formed on the peripheral circuits of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is formed either in the semiconductor substrate as a trench capacitor, or is built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip, and to move the adjacent capacitors on memory cells closer together. Unfortunately, as the cell size decreases, it becomes increasingly more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit. As cell density increases and cell area decreases, it is also necessary to make the capacitors closer together. This results in increased parasitic capacitance between adjacent capacitors and can disturb the data retention (charge) on the capacitor.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance while decreasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors in the vertical direction over the access transistors within each cell area to increase the capacitance of the individual capacitors by increasing the capacitor area in the vertical direction. However, when these vertical stacked capacitors are formed by making bottom electrodes in recesses in an insulating layer (having dielectric constant k), the increase in parasitic capacitance between adjacent capacitors can adversely affect the data retention.
The unwanted parasitic capacitance C.sub.p (C.sub.p =kA/d) between capacitors increases because of their close proximity (decreasing spacing d), and because the effective area A also increases between adjacent capacitors.
Several methods have been reported that increase the capacitance of the individual capacitors, but do not address the problem associated with the parasitic capacitance C.sub.p due to the close proximity of adjacent capacitors. For example, in U.S. Pat. No. 5,811,331 to Ying et al., a method is taught for making cylindrical capacitors with improved void-free insulation and better photolithographic overlay tolerances. In U.S. Pat. No. 5,851,877 to Ho et al., a method of making crown-shaped capacitors is described in which the formation of a polymer residue on the sidewalls of the bottom electrodes during etching is utilized as an etch mask. In U.S. Pat. No. 5,858829 to Chen, a method is described for making cylindrical-shaped capacitors self-aligned to bit lines formed from electrically conducting sidewall spacers (split bit line) that reduces cell area. Still another method for reducing RC time constant by reducing the capacitance C is taught in U.S. Pat. No. 5,858,869 to Chen et al., in which a low-dielectric-constant (low-k) oxide and polymer are used between metal lines (interconnections).
Although there has been considerable work done to increase the capacitor area on these miniature stacked capacitors, there is still a need to fabricate an array of DRAM cells with minimum parasitic capacitance between adjacent capacitors. This will become exceptionally important as the cell area decreases on future gigabit DRAM circuits anticipated for production after the year 2000.